Computers address physical memory to obtain both program instructions and data. Physical memory inturn provides data and program instructions to the processing unit of a computer. Physical memory space is limited in size to the physical memory size of the hardware within the computer.
In order to develop a computer with a memory space larger than the physical memory space, many computers utilize the concept of a virtual memory space. Typically, a virtual memory space is several orders of magnitude larger than the actual physical memory size. Most computers with a virtual memory space are operated by translating virtual memory addresses to physical memory addresses.
Cache memory subsystems improve the performance of computer systems. Traditionally, cache memory subsystems are physical memory address based. Some computers have virtual address caches. A speed advantage in using a virtual address cache memory subsystem exists. For virtual address caches, the speed advantage arises from the fact that the cache look-up may begin before completing a virtual-to-physical memory address translation.
Although virtual address caches have an inherent speed advantage over physical address caches, the complexities of virtual address caches limit their application. For example, one problem with virtual address caches relates to maintaining correct data protection information for cached data. Data protection information is usually defined for a page or segment of memory and includes such items as read privileges, write privileges, execution privileges over multiple privilege levels, and data ownership. Caches (virtual and physically addressed) are structured with lines, and usually cache lines have a different organization than the page or segment organization. Therefore, developing schemes by which virtual address caches are updated for protection information changes has challenged computer designers.
One prior art approach to handling protection information changes with a computer system containing a virtual address cache relies on dedicated hardware which sequentially checks all the cache tag addresses and invalidates cache lines which correspond to data that has had a protection change. Typically, protection bits are associated with an entire page or segment of memory. Therefore, more than one cache line may need to be invalidated if a page's or segment's protection bits change. This checking process necessitates additional hardware, and prior art approaches lock out program execution cache addressing while the checking of the tags commences, resulting in a performance penalty.